Conventionally, functions and features of a large-scale circuit are verified by simulating a designed circuit. Verification using a simulation is effective to extract failures earlier in a circuit design stage. However, a process time for the verification is a problem. Thus, in order to reduce calculation points and nodes which become factors increasing the time of the simulation, a designer has changed an abstraction level of a model for each of blocks forming a circuit, based on experiences of a circuit design and verification of the designer concerning verification contents and blocks related to the verification contents.
In this verification circumstance, as a technology for changing the abstraction level of the model of a circuit block, a part of a verification target is specified at a given verification level based on a simulation result of the highest verification level. As another technology, for a portion possible to be replaced with a function description in circuit element information in input data, the function description is selected from a function description database to replace the portion. As a further technology, a timing of changing the abstraction level of a circuit is determined by analyzing the circuit in a semiconductor integrated circuit based on a circuit database. At the determined timing, a simulation is conducted by switching to the entire circuit simulation or to a partial circuit simulation in which a portion, which is not needed to be analyzed, is regarded as a black box.
In the simulation, an operation of the circuit is verified in accordance with the verification contents. Depending on the verification contents, a path in which a signal propagates in the circuit becomes different. Also, recently, when the circuit becomes a larger scale, the path becomes more complicated.
In the above described conventional technologies, in order to reduce a process workload of the simulation, a verification target is determined beforehand to change a detail level or the abstraction level, or the number of elements is reduced beforehand by changing to an equivalent circuit based on an estimation result of availability of the simulation.
Therefore, in the path in the circuit, when the simulation is executed in accordance with the verification contents, there is a problem in which a block to be verified with a low abstraction level of a model may be verified with a high abstraction level. Also, a block to be verified with a high abstraction level of the model may be verified with a low abstraction level.